1. Field of the Invention
The present invention relates to a switching power supply circuit. Particularly, it relates to a switching power supply circuit provided with a power factor controller circuit which can stably control switching operation within a wide input voltage range.
2. Description of the Background Art
In lots of electronic devices supplied with commercial alternating current (AC) power supplies (in the range of from AC 100 V to 240 V), switching power supply circuits are used in order to obtain direct current (DC) power supplies driving internal electronic circuits. Therefore, a rectifier circuit for converting a commercial AC power supply into a direct current is required in such a switching power supply circuit. A current flows into a smoothing capacitor connected in a subsequent stage to the rectifier circuit only when an input voltage reaches the vicinity of the peak exceeding the voltage of the smoothing capacitor. Therefore, there is a problem that high frequency current and voltage components occur as high frequency noise sources and a power factor deteriorates.
The power factor means a value which is obtained by dividing input effective power Pi (W) by apparent power. The input effective power Pi (W) is the product of an input voltage and an in-phase component of an input current in an AC circuit. The apparent power is the product of an effective value of the input voltage and an effective value of the input current. The effective power is obtained by multiplying the apparent power by a coefficient (power factor) depending on a load. When a simple resistance load is connected to AC 100 V, a voltage waveform and a current waveform are in phase with each other. Therefore, the power factor becomes 1. However, in a switching power supply, a current phase may delay with respect to a voltage phase due to another load factor than the resistance load. Thus, a part of the effective power may lack correspondingly to the delay. For that reason, it is necessary to prevent deterioration of the power factor by means of a power factor controller (PFC) circuit to thereby suppress the decrease of the effective power or the useless increase of the apparent power for obtaining necessary effective power. At the same time, it is necessary to suppress high frequency noise.
The power factor controller circuit is a circuit which makes an AC input current waveform in phase with an AC input voltage waveform rectified by the rectifier circuit in the switching power supply circuit to thereby improve the power factor to be close to 1. The power factor controller circuit further controls a high-frequency current or voltage which may lead to generation of harmful EMI (Electro-Magnetic Interference) or breakdown of a device.
FIG. 9 is a circuit diagram showing a switching power supply circuit using a background-art power factor controller circuit. FIG. 10 is a circuit diagram schematically showing the configuration of a background-art lamp oscillator. Incidentally, in the following description, the same symbols may be used for the names of terminals and voltages, signals, etc. in the terminals respectively.
As shown in FIG. 9, in the switching power supply circuit, an AC input voltage is full-wave rectified by a full-wave rectifier 1, and one end of a capacitor 2 is connected to an output end of the full-wave rectifier 1 so that a high frequency component caused by switching operation can be removed by the capacitor 2. In addition, one end of a primary-side inductor 3 of a transformer T serving as an inductance element is connected to the output end of the full-wave rectifier 1. A step-up circuit including an MOSFET (Metal-Oxide Semiconductor Field Effect Transistor, hereinafter simply referred to as output transistor) 4 serving as a switching element, a diode 5 and a capacitor 6 is provided between the other end of the primary-side inductor 3 of the transformer T and a reference potential (ground potential). Incidentally, the diode 5 and the capacitor 6 form a DC voltage generating portion which rectifies and smoothes a current from the primary-side inductor 3 of the transformer T and obtains a predetermined DC output voltage. A rectified voltage outputted from the full-wave rectifier 1 is stepped up and rectified by the aforementioned step-up circuit, so that, for example, a DC output voltage of about 400 V can be supplied to a load (not shown) connected between an output terminal 7 and the ground.
A power factor controller circuit 100 is constituted by an integrated circuit in which various functions are provided integrally. The power factor controller circuit 100 performs control called critical control system to turn ON the output transistor 4 when the current of the primary-side inductor 3 of the transformer T becomes zero in an OFF-time of the output transistor 4. The critical control system is used in an electronic device consuming small electric power, for example, to be not higher than about 250 W.
The power factor controller circuit 100 has an FB terminal, an IS terminal, an OUT terminal, a ZCD (Zero-Crossing Detection) terminal, an RT terminal, and a COMP terminal as external connection terminals. The FB terminal is connected to a connection point between resistors R4 and R5 which are connected in series between the output terminal 7 and the ground. The FB terminal serves as a feedback signal inputting terminal for feeding back the output voltage. A current detecting resistor R3 is connected between the IS terminal and the ground. The IS terminal serves as a terminal for converting a current flowing into the current detecting resistor R3 into a voltage and detecting a current flowing into the output transistor 4. The OUT terminal serves as a terminal for outputting a signal driving a gate of the MOSFET constituting the output transistor 4 so that ON/OFF of the MOSFET can be controlled in accordance with the output from the OUT terminal. The ZCD terminal is connected to one end of a secondary-side inductor 8 through a resistor R2. The other end of the secondary-side inductor 8 of the transformer T is grounded. The ZCD terminal serves as a terminal for inputting a zero-cross signal generated by the secondary-side inductor 8 of the transformer T. The RT terminal serves as a resistor connecting terminal determining an oscillation waveform. A timing resistor R1, of which one end is grounded is connected to the RT terminal. The RT terminal is a terminal for generating a sawtooth wave signal having a slope corresponding to a resistance value of the timing resistor R1. The COMP terminal serves as a terminal for connecting a phase compensation element. The COMP terminal is grounded through a capacitor C1. A series circuit between a resistor R6 and a capacitor C2 is connected in parallel with the capacitor C1. The capacitors C1 and C2 and the resistor R6 form a phase compensation circuit. In addition thereto, the power factor controller circuit 100 is also provided with a power supply voltage input VCC terminal, a ground GND terminal, etc., which are not shown.
An error amplifier 11 which amplifies and outputs a difference between a detection value of an output voltage inputted to the FB terminal and a reference voltage Vref, and a PWM (Pulse Width Modulation) comparator 12 are provided internally in the power factor controller circuit 100. Moreover, the power factor controller circuit 100 has a lamp oscillator 13, OR circuits 14a and 14b, an RS flip-flop 15, a ZCD (Zero-Crossing Detection) comparator 16, a one-shot circuit 17, and a restart timer 18. The power factor controller circuit 100 further has an OVP (Overvoltage Protection) comparator 19 used for protecting an overvoltage, and an OCP (OverCurrent Protection) comparator 20 used for detecting an overcurrent.
A non-inverting input of the error amplifier 11 of the power factor controller circuit 100 receives the reference voltage Vref. The FB terminal is connected to an inverting input of the error amplifier 11. An output of the error amplifier 11 is connected to the COMP terminal and an inverting input of the PWM comparator 12. An output of the PWM comparator 12 is connected to a reset terminal of the RS flip-flop 15 through the OR circuit 14b. The lamp oscillator 13 is connected to the external timing resistor R1 through the RT terminal and generates a sawtooth wave signal S1 having a slope corresponding to the resistance value of the timing resistor R1. The sawtooth wave signal is supplied to a non-inverting input of the PWM comparator 12.
A non-inverting input side of the ZCD comparator 16 receives a reference voltage Vzcd. An inverting input side of the ZCD comparator 16 is connected to the ZCD terminal. An output of the ZCD comparator 16 is connected to the one-shot circuit 17 and the restart timer 18. An output of the one-shot circuit 17 and an output of the restart timer 18 are supplied to a set terminal of the RS flip-flop 15 through the OR circuit 14a. An output signal S0 of the RS flip-flop 15 is supplied to the gate terminal of the output transistor 4 through the OUT terminal.
In addition, an inverting input side of the OVP comparator 19 receives a reference voltage Vovp. A non-inverting input side of the OVP comparator 19 is connected to the FB terminal. An output of the OVP comparator 19 is connected to the reset terminal of the RS flip-flop 15 through the OR circuit 14b. Further, an inverting input side of the OCP comparator 20 receives a reference voltage Vocp. A non-inverting input side of the OCP comparator 20 is connected to the IS terminal. An output of the OCP comparator 20 is connected to the reset terminal of the RS flip-flop 15 through the OR circuit 14b. 
Here, as shown in FIG. 10, the lamp oscillator 13 has an operational amplifier 1301, a reference voltage source 1302 and an N channel MOSFET 1303, which form a circuit outputting a constant voltage to the RT terminal to apply a constant current to the timing resistor R1. That is, two inputs of the operational amplifier 1301 are virtually short-circuited to apply, to the RT terminal, the constant voltage outputted from the reference voltage source 1302, and a current obtained by dividing a difference between the applied constant voltage and a voltage outputted from a reference voltage source 1309, which will be described later, by the resistance value of the timing resistor R1 flows into the timing resistor R1. The constant current flowing into the timing resistor R1 is returned as a current i1 by a current mirror circuit constituted by P channel MOSFETs 1304 and 1305. The current i1 is supplied to a circuit which has a P channel MOSFET 1306, an inverter 1307, an N channel MOSFET 1308, the reference voltage source 1309, and a capacitor 1310. An input of the inverter 1307 is connected to an S0 terminal to which the output signal S0 of the RS flip-flop 15 is supplied. An output of the inverter 1307 is connected to a gate terminal of the MOSFET 1306 and a gate terminal of the MOSFET 1308. A drain terminal of the MOSFET 1306 and a drain terminal of the MOSFET 1308 are connected to one end of the capacitor 1310 and an S1 terminal. The other end of the capacitor 1310 is connected to a connection point between a source terminal of the MOSFET 1308 and the reference voltage source 1309.
In the lamp oscillator 13, the capacitor 1310 is charged with the constant current i1 by the MOSFET 1306 when the output transistor 4 is ON (the output signal S0 is in an H (High) level) in response to the output signal S0 of the RS flip-flop 15. On the other hand, when the output transistor 4 turns OFF (the output signal S0 turns to an L (Low) level), electric charges stored in the capacitor 1310 are rapidly discharged by the MOSFET 1308. In this manner, the lamp oscillator 13 outputs, to the terminal S1, the sawtooth wave signal S1 having the slope depending on the timing resistor R1 with reference to the voltage of the reference voltage source 1309.
Next, operation of the switching power supply circuit having the aforementioned configuration will be described in detail.
FIG. 11 is a view for explaining an operation when the RS flip-flop is set. FIG. 12 is a view for explaining an operation when the RS flip-flop is reset. FIG. 13 is a view for explaining the relation between the change of an error signal Verr caused by the change of a load and a signal outputted from the OUT terminal. In addition, FIG. 14 is a view for explaining factors causing the change of the error signal during a light load. FIG. 15 is a view for explaining the influence caused by the change of the error signal during the light load.
The ZCD comparator 16 detects a timing at which an inductor current flowing into the primary-side inductor 3 of the transformer T in the step-up circuit becomes zero. A voltage value of the ZCD terminal is in an L level when the inductor current flowing into the inductor 3 is increasing or when the inductor current is zero. On the other hand, the voltage value of the ZCD terminal is in an H level when the inductor current is decreasing. When the ZCD comparator 16 monitors the voltage of the ZCD terminal and detects the falling of the voltage, i.e. detects zero as the inductor current, the output of the ZCD comparator 16 turns to an H level, as shown in FIG. 11. Upon reception of the H level signal, the one-shot circuit 17 outputs a one-shot pulse as a set signal to the RS flip-flop 15 through the OR circuit 14a. In this manner, the RS flip-flop 15 outputs and supplies an H level output signal S0 to the gate terminal of the output transistor 4 through the OUT terminal to thereby turn ON the output transistor 4. On this occasion, the output signal of the ZCD comparator 16 triggers the restart timer 18. During normal ON/OFF operation of the output transistor 4, the restart timer 18 is triggered by a next output signal of the ZCD comparator 16 before the time is out. Accordingly, the restart timer 18 maintains output of an L level signal.
Here, when, for example, the OVP comparator 19 detects an overvoltage of the output voltage at a time instant t1, the RS flip-flop 15 changes the reset signal to an H level and suspends switching operation of the output transistor 4 (to keep the output transistor 4 OFF) on and after the time instant t1. Even in this case, the restart timer 18 is triggered to start to count time (time instant t2) when the ZCD comparator 16 detects the falling of the voltage of the ZCD terminal. When the time is out (time instant t3) during the suspension of the switching operation in the output transistor 4, the restart timer 18 outputs an H level signal. On this occasion, the RS flip-flop 15 is operating with reset priority due to the reset signal inputted from the OVP comparator 19. Accordingly, the output signal S0 is kept at the L level as it is.
When the output voltage is then resumed normally and the output of the OVP comparator 19 turns to an L level at a time instant t4, the RS flip-flop 15 is set by the H level output signal of the restart timer 18 and outputs an H level signal to the OUT terminal. Next, when the output transistor 4 turns OFF and the voltage of the ZCD terminal rises at a time instant t5, the output signal of the restart timer 18 turns to an L level and the restart timer 18 is triggered to start to count time at the falling of a next voltage of the ZCD terminal (time instant t6).
The output signal S0 of the RS flip-flop 15 is also inputted to the lamp oscillator 13. In the lamp oscillator 13, at the same timing as the timing when the output transistor 4 turns ON, the MOSFET 1306 turns ON to start to charge the capacitor 1310 with the current i1 so that the capacitor 1310 can start to generate the sawtooth wave signal S1. When the output transistor 4 turns OFF, the MOSFET 1308 turns ON to discharge electric charges of the capacitor 1310 so that the lamp oscillator 13 can suspend generation of the sawtooth wave signal S1. Thus, in sync with the ON/OFF of the output transistor 4, the lamp oscillator 13 generates the sawtooth wave signal S1 as shown in FIG. 12. The sawtooth wave signal S1 is compared with an error signal Verr by the PWM comparator 12 and the reset signal of the RS flip-flop 15 is generated.
When a difference between a feedback voltage, in which a DC voltage outputted from the output terminal 7 is divided by the resistors R4 and R5 and fed back to the FB terminal, and the reference voltage Vref is amplified by the error amplifier 11, an error signal Verr is generated. In the PWM comparator 12, the error signal Verr and the sawtooth wave signal S1 from the lamp oscillator 13 are compared with each other, and a reset signal is outputted to the RS flip-flop 15 when the sawtooth wave signal S1 reaches the error signal Verr. Thus, the output signal S0 of the RS flip-flop 15 turns to an L level. When the L level output signal S0 is outputted from the OUT terminal, the output transistor 4 turns OFF. Incidentally, the change of an inductor current Iind flowing into the primary-side inductor 3 of the transformer T, the change of the voltage of the ZCD terminal, and the change of a drain-source voltage Vds of the output transistor 4 are also shown correspondingly to the voltage of the OUT terminal in FIG. 12.
The error signal Verr expresses excess or shortage of electric power outputted from the output terminal 7. The error signal Verr fluctuates vertically due to the magnitude of a load. That is, the error signal Verr becomes high in the case where the load is heavy, and becomes low in the case where the load is light. The slope of the sawtooth wave signal S1 is constant. Accordingly, as shown in FIG. 13, the time until the sawtooth wave signal S1 reaches the error signal Verr is long in the case where the load is heavy. Therefore, a timing when the reset signal is outputted to the RS flip-flop 15 is delayed correspondingly. Thus, the ON width (ON-time) of the output transistor 4 becomes wide so that a large amount of energy can be sent by the output terminal 7. On the other hand, the time until the sawtooth wave signal S1 reaches the error signal Verr is short in the case where the load is light. Consequently, the ON width of the output transistor 4 becomes narrow.
When the magnitude of the load connected to the output terminal 7 of the switching power supply circuit is constant here, the error signal Verr is also constant basically. The ON width of the output transistor 4 corresponds to a time required for the sawtooth wave signal S1 to start from the reference value (reference voltage 1309) and reach the error signal Verr. Accordingly, when the error signal Verr is constant, the ON width can be controlled fixedly.
However, since the input of the switching power supply circuit is an AC voltage, the voltage at the opposite ends of the primary-side inductor 3 changes due to a phase angle of the AC voltage. Therefore, the slope of the inductor current Iind flowing into the primary-side inductor 3 of the transformer T changes depending on the input voltage. As a result, the peak value of the inductor current (i.e. a current value at a timing when the output transistor 4 turns OFF) becomes an AC waveform.
In addition, when the AC input voltage is converted into a DC output voltage, a ripple voltage depending on the cycle of the AC input occurs in the output voltage. The ripple voltage increases as the capacitance value of the capacitor 6 provided in the output terminal 7 decreases. Recently, with the reduction of the price of an electronic device, the capacitance value of the capacitor 6 provided in the output terminal 7 tends to decrease in order to reduce the cost of a power supply, and the ripple voltage therefore tends to increase. When the ripple voltage increases, a ripple voltage of the error signal Verr outputted from the error amplifier 11 also increases.
That is, as shown in FIG. 14, when a voltage Vac full-wave rectified by the full-wave rectifier 1 is inputted, a current Iac flowing into the primary-side inductor 3 of the transformer T and the capacitor 6 changes in a cycle twice as fast as the voltage Vac, and a charging voltage of the capacitor 6 receiving the current Iac, that is, the output voltage also changes in the cycle twice as fast as the voltage Vac. When the change of the output voltage is inputted to the error amplifier 11 through the FB terminal, the error amplifier 11 outputs an error signal Verr having an unstable waveform fluctuating with respect to an average value. Therefore, the PWM comparator 12 compares the sawtooth wave signal S1 from the lamp oscillator 13 and the unstable error signal Verr with each other, and generates a reset signal for turning OFF the output transistor 4. In this case, normal operation may be performed to generate a reset signal to output an output signal S0 for turning ON/OFF the output transistor 4 to the OUT terminal or abnormal operation may be performed to continuously output a reset signal so as not to output an output signal S0 to the OUT terminal even when the ZCD terminal has turned to an L level.
This is conspicuous when the error signal Verr is low during a light load and control is made to narrow the ON width of the output transistor 4 and reduce the energy to be sent to the output terminal 7. In this case, the error signal Verr and a lower limit (reference voltage 1309) of the sawtooth wave signal S1 are close to each other as shown in FIG. 15. Therefore, when an AC component is superimposed on the error signal Verr, the error signal Verr may be lower than the lower limit of the sawtooth wave signal S1. In the period in which the error signal Verr is lower than the lower limit of the sawtooth wave signal S1, the output of the PWM comparator 12 is always in an H level and the reset signal is sent to the RS flip-flop 15 continuously. Accordingly, the switching power supply circuit suspends the switching operation. Thus, the period in which the switching operation is being performed and the period in which the switching operation is being suspended are generated. The switching power supply circuit operates intermittently. When the cycle of the intermittent operation is in an audible range, the operation may be an unstable burst operation, causing noise.
Since one switching power supply circuit is used to support AC input voltages different from one country to another, the power factor controller circuit has to output a constant voltage from a wide input voltage range of from AC 90 V to AC 264 V. On this occasion, when a gain is designed to be high enough to take a sufficiently large load from a low input voltage, the gain may be too high to perform stable operation under a low load with a high input voltage. It is therefore difficult to perform stable operation in the wide input voltage range. Therefore, for example, as described in US Unexamined Patent Application Publication No. 2013/0121047, there is generally used a method in which feed-forward control is applied to the input voltage to increase the gain when the input voltage is low and to reduce the gain when the input voltage is high so that a switching power supply circuit can be operated stably within a wide input voltage range.
However, in the feed-forward control on the input voltage for eliminating unstable operation, the input voltage has to be monitored. Therefore, there is a problem that standby power may deteriorate due to losses in the resistors dividing the input voltage and the number of pins in a control IC of the power factor controller circuit may increase for monitoring the input voltage.